1. Field of the Invention
The present invention relates to a process for fabricating a memory device. More particularly, the present invention relates to a process for fabricating a dynamic random access memory (DRAM).
2. Description of Related Art
Generally, the memory unit of a dynamic random access memory (DRAM) includes a transistor and a capacitor. As the device dimension is gradually miniaturized, the space available for accommodating a capacitor in a DRAM device is also shrunk. Therefore, a trench capacitor formed in a substrate that can effectively utilize the space available in the substrate satisfies the current market demand. At present, DRAM devices are frequently fabricated with deep-trench (DT) capacitors having large capacitance for better performance.
FIG. 1 through FIG. 4 are schematic views illustrating the steps for fabricating a conventional dynamic random access memory (DRAM). Sub-diagrams (a) of FIG. 1 through FIG. 4 illustrate schematic top views and sub-diagrams (b) of FIG. 1 through FIG. 4 illustrate schematic cross-sectional views along line I-I′ of FIG. 1(a) through FIG. 4(a).
First, please refer to FIG. 1. A plurality of trenches 102 are formed in a substrate 100. Further, a trench capacitor 104 is formed in each trench 102, and a pillar oxidation layer 106 is formed on the trench capacitor 104. In addition, a silicon nitride layer 108 is formed on the substrate 100 to conformably cover the pillar oxidation layer 106.
Next, please refer to FIG. 2. A silicon layer 110 is formed over the substrate 100 to conformably cover the silicon nitride layer 108. The material used for fabricating the silicon layer 110 is, for example, polysilicon or amorphous silicon. Thereafter, a tilt angle ion implantation process 112 is performed to form a doped region 113 in a portion of the silicon layer 110 disposed on two sides of the pillar oxidation layer 106. As a result, the etch rate of the doped region 113 is slower than that of the silicon layer 110 that is not covered by the doped region 113.
Afterward, please refer to FIG. 3. An etching process is performed to remove the silicon layer 110 but retain the doped region 113. Subsequently, please refer to FIG. 4. An oxidation process is performed to the doped region 113 to form oxidation spacers 114 containing both silicon layer and oxidation layer. Then, an active area (AA) 116 is defined between two adjacent trenches 102. Next, a transistor (not shown) is formed in the active area 116 and the source/drain region (not shown) of this transistor is formed below the oxidation spacers 114 in the substrate 100.
After the transistor is fabricated, the oxidation spacers 114 are removed to form a bit line contact (not shown) to electrically connect the source/drain region of the transistor to the bit line to be formed. More specifically, the region of the above-mentioned oxidation spacers is the landing area for the bit line contact. Nevertheless, according to the above-mentioned prior art, if the pattern of the bit line contact opening cannot be defined within the range of length for the oxidation spacers 114, overlay errors that lead to misalignment issues are resulted. The aforementioned misalignment problem shifts the bit line contact to be formed to the edge of the transistor gate, causing a short between the bit line contact and the transistor gate and thus affecting the device performance.
Therefore, it has become one of the major goals in the development of the semiconductor industry to produce a high quality device that prevents the aforementioned problem.